Hooi, L. (2017). Configurable 2 bits per cycle successive approximation register for analog to digital converter on FPGA. Institute of Electrical and Electronics Engineers Inc.
Chicago Style CitationHooi, L.Y. Configurable 2 Bits Per Cycle Successive Approximation Register for Analog to Digital Converter On FPGA. Institute of Electrical and Electronics Engineers Inc, 2017.
MLA CitationHooi, L.Y. Configurable 2 Bits Per Cycle Successive Approximation Register for Analog to Digital Converter On FPGA. Institute of Electrical and Electronics Engineers Inc, 2017.
Warning: These citations may not always be 100% accurate.