A hybrid delay design-for-testability for nonseparable RTL controller-data path circuits

by Shaheen, A.-U.-R., Hussin, F.A., Hamid, N.H.
Published 2017
Institution: Universiti Teknologi Petronas

Delay design-for-testability for functional RTL circuits

by Shaheen, A.-U.-R., Hussin, F.A., Hamid, N.H.
Published 2015
Institution: Universiti Teknologi Petronas

Delay design-for-testability for functional RTL circuits

by Shaheen, A.-U.-R., Hussin, F.A., Hamid, N.H.
Published 2015
Institution: Universiti Teknologi Petronas

False path identification algorithm framework for nonseparable controller-data path circuits

by Shaheen, A.-U.-R., Hussin, F.A., Hamid, N.H.
Published 2017
Institution: Universiti Teknologi Petronas

Automatic generation of test instructions for path delay faults based-on stuck-at fault in processor cores using assignment decision diagram

by Shaheen, A.-U.-R., Hussin, F.A., Hamid, N.H., Ali, N.B.Z.
Published 2014
Institution: Universiti Teknologi Petronas