A 2.4/5.2-GHz Concurrent Dual-Band CMOS Low Noise Amplifier

A concurrent dual-band low-noise amplifier (LNA) targeted for W-LAN IEEE 802.11 a/b/g standards is designed using 0.13- μm CMOS process. To attain the power-constrained simultaneous noise and input matching at 2.4 and 5.2 GHz, cascode common source inductive degeneration topology is adopted. The LNA...

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Main Authors: Sattar, S., Zulkifli, T.Z.A.
Format: Article
Institution: Universiti Teknologi Petronas
Record Id / ISBN-0: utp-eprints.19351 /
Published: Institute of Electrical and Electronics Engineers Inc. 2017
Online Access: https://www.scopus.com/inward/record.uri?eid=2-s2.0-85030784488&doi=10.1109%2fACCESS.2017.2756985&partnerID=40&md5=1c7bf4f567322f8fa1eb324f1ce2b742
http://eprints.utp.edu.my/19351/
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id utp-eprints.19351
recordtype eprints
spelling utp-eprints.193512018-04-20T00:21:14Z A 2.4/5.2-GHz Concurrent Dual-Band CMOS Low Noise Amplifier Sattar, S. Zulkifli, T.Z.A. A concurrent dual-band low-noise amplifier (LNA) targeted for W-LAN IEEE 802.11 a/b/g standards is designed using 0.13- μm CMOS process. To attain the power-constrained simultaneous noise and input matching at 2.4 and 5.2 GHz, cascode common source inductive degeneration topology is adopted. The LNA achieves input reflection coefficients of -16.8 and -19.4 dB, forward gains of 19.3 and 17.5 dB at 2.4 and 5.2 GHz, respectively. Furthermore, the LNA exhibits noise figures of 3.2 and 3.3 dB with input 1-dB compression points of -29.6 and -28.2 dBm, while third-order input intercept points of -20.1 and -18.1 dBm at 2.4 and 5.2 GHz, respectively. The LNA dissipates 2.4 mW of power from a 1.2-V supply. © 2013 IEEE. Institute of Electrical and Electronics Engineers Inc. 2017 Article PeerReviewed https://www.scopus.com/inward/record.uri?eid=2-s2.0-85030784488&doi=10.1109%2fACCESS.2017.2756985&partnerID=40&md5=1c7bf4f567322f8fa1eb324f1ce2b742 Sattar, S. and Zulkifli, T.Z.A. (2017) A 2.4/5.2-GHz Concurrent Dual-Band CMOS Low Noise Amplifier. IEEE Access, 5 . pp. 21148-21156. http://eprints.utp.edu.my/19351/
institution Universiti Teknologi Petronas
collection UTP Institutional Repository
description A concurrent dual-band low-noise amplifier (LNA) targeted for W-LAN IEEE 802.11 a/b/g standards is designed using 0.13- μm CMOS process. To attain the power-constrained simultaneous noise and input matching at 2.4 and 5.2 GHz, cascode common source inductive degeneration topology is adopted. The LNA achieves input reflection coefficients of -16.8 and -19.4 dB, forward gains of 19.3 and 17.5 dB at 2.4 and 5.2 GHz, respectively. Furthermore, the LNA exhibits noise figures of 3.2 and 3.3 dB with input 1-dB compression points of -29.6 and -28.2 dBm, while third-order input intercept points of -20.1 and -18.1 dBm at 2.4 and 5.2 GHz, respectively. The LNA dissipates 2.4 mW of power from a 1.2-V supply. © 2013 IEEE.
format Article
author Sattar, S.
Zulkifli, T.Z.A.
spellingShingle Sattar, S.
Zulkifli, T.Z.A.
A 2.4/5.2-GHz Concurrent Dual-Band CMOS Low Noise Amplifier
author_sort Sattar, S.
title A 2.4/5.2-GHz Concurrent Dual-Band CMOS Low Noise Amplifier
title_short A 2.4/5.2-GHz Concurrent Dual-Band CMOS Low Noise Amplifier
title_full A 2.4/5.2-GHz Concurrent Dual-Band CMOS Low Noise Amplifier
title_fullStr A 2.4/5.2-GHz Concurrent Dual-Band CMOS Low Noise Amplifier
title_full_unstemmed A 2.4/5.2-GHz Concurrent Dual-Band CMOS Low Noise Amplifier
title_sort 2.4/5.2-ghz concurrent dual-band cmos low noise amplifier
publisher Institute of Electrical and Electronics Engineers Inc.
publishDate 2017
url https://www.scopus.com/inward/record.uri?eid=2-s2.0-85030784488&doi=10.1109%2fACCESS.2017.2756985&partnerID=40&md5=1c7bf4f567322f8fa1eb324f1ce2b742
http://eprints.utp.edu.my/19351/
_version_ 1741196192908312576
score 11.62408

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