VCO DEVELOPMENT USING 130nm CMOS TECHNOLOGY

This dissertation focuses on the simulation of a VCO that is optimized for its phase noise properties by utilizing Cadence tools. Besides, a detailed study on the main causes of phase noise in a VCO and techniques of improving the VCO’s phase noise was also conducted in the midst of VCO design. A to...

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Main Author: ARULNATHAN, JONATHAN
Format: Final Year Project
Language: English
Institution: Universiti Teknologi Petronas
Record Id / ISBN-0: utp-utpedia.19142 /
Published: 2018
Online Access: http://utpedia.utp.edu.my/19142/1/22379%20Jonathan%20Arulnathan%20FYP%20Final%20Report.pdf
http://utpedia.utp.edu.my/19142/
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spelling utp-utpedia.191422019-06-20T11:06:48Z http://utpedia.utp.edu.my/19142/ VCO DEVELOPMENT USING 130nm CMOS TECHNOLOGY ARULNATHAN, JONATHAN This dissertation focuses on the simulation of a VCO that is optimized for its phase noise properties by utilizing Cadence tools. Besides, a detailed study on the main causes of phase noise in a VCO and techniques of improving the VCO’s phase noise was also conducted in the midst of VCO design. A top-down approach was employed for the design process whereas a bottom-up approached was employed for verification purposes to ensure robustness of the design using Silterra 130nm CMOS process technology. As a result, a fully CMOS based VCO operating at 5GHz centre frequency was designed using a PMOS based varactor for tuning purposes. Overall, the VCO has been reported to have a nominal phase noise of -133.38 dBc/Hz at 10 MHz with 10% tuning range using 1.2V supply voltage and 5.23 mA current. During power down mode, the VCO has leakage current of 3.598pA. The VCO was tested across supply voltage and temperature variations for its robustness. 2018-09 Final Year Project NonPeerReviewed application/pdf en http://utpedia.utp.edu.my/19142/1/22379%20Jonathan%20Arulnathan%20FYP%20Final%20Report.pdf ARULNATHAN, JONATHAN (2018) VCO DEVELOPMENT USING 130nm CMOS TECHNOLOGY. UNSPECIFIED.
institution Universiti Teknologi Petronas
collection UTPedia
language English
description This dissertation focuses on the simulation of a VCO that is optimized for its phase noise properties by utilizing Cadence tools. Besides, a detailed study on the main causes of phase noise in a VCO and techniques of improving the VCO’s phase noise was also conducted in the midst of VCO design. A top-down approach was employed for the design process whereas a bottom-up approached was employed for verification purposes to ensure robustness of the design using Silterra 130nm CMOS process technology. As a result, a fully CMOS based VCO operating at 5GHz centre frequency was designed using a PMOS based varactor for tuning purposes. Overall, the VCO has been reported to have a nominal phase noise of -133.38 dBc/Hz at 10 MHz with 10% tuning range using 1.2V supply voltage and 5.23 mA current. During power down mode, the VCO has leakage current of 3.598pA. The VCO was tested across supply voltage and temperature variations for its robustness.
format Final Year Project
author ARULNATHAN, JONATHAN
spellingShingle ARULNATHAN, JONATHAN
VCO DEVELOPMENT USING 130nm CMOS TECHNOLOGY
author_sort ARULNATHAN, JONATHAN
title VCO DEVELOPMENT USING 130nm CMOS TECHNOLOGY
title_short VCO DEVELOPMENT USING 130nm CMOS TECHNOLOGY
title_full VCO DEVELOPMENT USING 130nm CMOS TECHNOLOGY
title_fullStr VCO DEVELOPMENT USING 130nm CMOS TECHNOLOGY
title_full_unstemmed VCO DEVELOPMENT USING 130nm CMOS TECHNOLOGY
title_sort vco development using 130nm cmos technology
publishDate 2018
url http://utpedia.utp.edu.my/19142/1/22379%20Jonathan%20Arulnathan%20FYP%20Final%20Report.pdf
http://utpedia.utp.edu.my/19142/
_version_ 1741195455199444992
score 11.62408

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