PATH DELAY DESIGN-FOR-TESTABILITY USING SNOOPING FOR FUNCTIONAL REGISTER-TRANSFER LEVEL CIRCUITS
Testing of VLSI circuits is important to ensure the reliability of digital systems. Due to the advancement in process technology, more performance defects occur. Path delay testing ensures the timing accuracy and functional correctness of the VLSI circuits and has become crucial. The standard sca...
| Main Author: | SHAHEEN, ATEEQ-UR-REHMAN |
|---|---|
| Format: | Thesis |
| Language: | English |
| Institution: | Universiti Teknologi Petronas |
| Record Id / ISBN-0: | utp-utpedia.22054 / |
| Published: |
2017
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| Subjects: | |
| Online Access: |
http://utpedia.utp.edu.my/22054/1/PATH%20DELAY%20DESIGN-FOR-TESTABILITY%20USING%20SNOOPING%20FOR%20FUNCTIONAL%20REGISTER-TRANSFER%20LEVEL%20CIRCUITS%20%28Ateeq-ur-Rehman%20Shaheen_G01838%29.pdf http://utpedia.utp.edu.my/22054/ |
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