Delay design-for-testability for functional RTL circuits
Design-for-testability (DFT) reduces the test complexity of sequential register-transfer-level (RTL) circuits. Only enhanced scan technique from the scan based approaches guarantee two-pattern testability with a large area and test time overhead. This paper proposes a path delay DFT technique for fu...
| Main Authors: | Shaheen, A.-U.-R., Hussin, F.A., Hamid, N.H. |
|---|---|
| Format: | Conference or Workshop Item |
| Institution: | Universiti Teknologi Petronas |
| Record Id / ISBN-0: | utp-eprints.25915 / |
| Published: |
Institute of Electrical and Electronics Engineers Inc.
2015
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| Online Access: |
https://www.scopus.com/inward/record.uri?eid=2-s2.0-84966570516&doi=10.1109%2fICITEED.2015.7408997&partnerID=40&md5=e785339cc2b5ab362d54d9b80623c537 http://eprints.utp.edu.my/25915/ |
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