Automatic generation of test instructions for path delay faults based-on stuck-at fault in processor cores using assignment decision diagram

This paper proposes a satisfiability-based automatic test instruction program generation to test the path delay faults using stuck-at fault in processor cores. Pre-computed test vectors are applied using the test instructions during normal processor execution. The proposed framework uses the assignm...

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Main Authors: Shaheen, A.-U.-R., Hussin, F.A., Hamid, N.H., Ali, N.B.Z.
Format: Conference or Workshop Item
Institution: Universiti Teknologi Petronas
Record Id / ISBN-0: utp-eprints.32104 /
Published: IEEE Computer Society 2014
Online Access: https://www.scopus.com/inward/record.uri?eid=2-s2.0-84906350466&doi=10.1109%2fICIAS.2014.6869530&partnerID=40&md5=4acc1a9593a3b00bf33b65139d9313d0
http://eprints.utp.edu.my/32104/
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spelling utp-eprints.321042022-03-29T04:34:38Z Automatic generation of test instructions for path delay faults based-on stuck-at fault in processor cores using assignment decision diagram Shaheen, A.-U.-R. Hussin, F.A. Hamid, N.H. Ali, N.B.Z. This paper proposes a satisfiability-based automatic test instruction program generation to test the path delay faults using stuck-at fault in processor cores. Pre-computed test vectors are applied using the test instructions during normal processor execution. The proposed framework uses the assignment decision diagram (ADD) which represents the structural description of the register transfer level (RTL) circuit to extract the paths. ADD representation and instruction set architecture (ISA) information eliminates the paths that are untestable by the instructions during path extraction. The satisfiability (SAT)-solver is used to generate the sequence from conjunctive normal form (CNF) to find the justification/propagation paths. Test sequence is mapped to ISA to generate the test instruction program. A parwan processor module is used to validate our approach. © 2014 IEEE. IEEE Computer Society 2014 Conference or Workshop Item NonPeerReviewed https://www.scopus.com/inward/record.uri?eid=2-s2.0-84906350466&doi=10.1109%2fICIAS.2014.6869530&partnerID=40&md5=4acc1a9593a3b00bf33b65139d9313d0 Shaheen, A.-U.-R. and Hussin, F.A. and Hamid, N.H. and Ali, N.B.Z. (2014) Automatic generation of test instructions for path delay faults based-on stuck-at fault in processor cores using assignment decision diagram. In: UNSPECIFIED. http://eprints.utp.edu.my/32104/
institution Universiti Teknologi Petronas
collection UTP Institutional Repository
description This paper proposes a satisfiability-based automatic test instruction program generation to test the path delay faults using stuck-at fault in processor cores. Pre-computed test vectors are applied using the test instructions during normal processor execution. The proposed framework uses the assignment decision diagram (ADD) which represents the structural description of the register transfer level (RTL) circuit to extract the paths. ADD representation and instruction set architecture (ISA) information eliminates the paths that are untestable by the instructions during path extraction. The satisfiability (SAT)-solver is used to generate the sequence from conjunctive normal form (CNF) to find the justification/propagation paths. Test sequence is mapped to ISA to generate the test instruction program. A parwan processor module is used to validate our approach. © 2014 IEEE.
format Conference or Workshop Item
author Shaheen, A.-U.-R.
Hussin, F.A.
Hamid, N.H.
Ali, N.B.Z.
spellingShingle Shaheen, A.-U.-R.
Hussin, F.A.
Hamid, N.H.
Ali, N.B.Z.
Automatic generation of test instructions for path delay faults based-on stuck-at fault in processor cores using assignment decision diagram
author_sort Shaheen, A.-U.-R.
title Automatic generation of test instructions for path delay faults based-on stuck-at fault in processor cores using assignment decision diagram
title_short Automatic generation of test instructions for path delay faults based-on stuck-at fault in processor cores using assignment decision diagram
title_full Automatic generation of test instructions for path delay faults based-on stuck-at fault in processor cores using assignment decision diagram
title_fullStr Automatic generation of test instructions for path delay faults based-on stuck-at fault in processor cores using assignment decision diagram
title_full_unstemmed Automatic generation of test instructions for path delay faults based-on stuck-at fault in processor cores using assignment decision diagram
title_sort automatic generation of test instructions for path delay faults based-on stuck-at fault in processor cores using assignment decision diagram
publisher IEEE Computer Society
publishDate 2014
url https://www.scopus.com/inward/record.uri?eid=2-s2.0-84906350466&doi=10.1109%2fICIAS.2014.6869530&partnerID=40&md5=4acc1a9593a3b00bf33b65139d9313d0
http://eprints.utp.edu.my/32104/
_version_ 1741197687078780928
score 11.62408

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