High throughput architecture for low density parity check (LDPC) encoder

This paper proposes a bit-wise matrix-vector multiplication in the optimization of a proposed low density parity check (LDPC) encoder. Investigation of this proposed architecture is done by implementing five code lengths using one IEEE 802.16e standard code rate. It is shown that the proposed archit...

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Main Authors: Anggraeni, S., Hussin, F.A., Jeoti, V.
Format: Conference or Workshop Item
Institution: Universiti Teknologi Petronas
Record Id / ISBN-0: utp-eprints.32545 /
Published: 2013
Online Access: https://www.scopus.com/inward/record.uri?eid=2-s2.0-84893175011&doi=10.1109%2fMWSCAS.2013.6674807&partnerID=40&md5=f7572e89e63b24d3968cc90517b9a2a3
http://eprints.utp.edu.my/32545/
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id utp-eprints.32545
recordtype eprints
spelling utp-eprints.325452022-03-29T14:06:03Z High throughput architecture for low density parity check (LDPC) encoder Anggraeni, S. Hussin, F.A. Jeoti, V. This paper proposes a bit-wise matrix-vector multiplication in the optimization of a proposed low density parity check (LDPC) encoder. Investigation of this proposed architecture is done by implementing five code lengths using one IEEE 802.16e standard code rate. It is shown that the proposed architecture outperforms other works in terms of information throughput ranging from 0.235 to 8.83 times higher. In term of ratio of throughput per area, the proposed method exceeds other works in the range of 1.19 to 6.54 times higher. © 2013 IEEE. 2013 Conference or Workshop Item NonPeerReviewed https://www.scopus.com/inward/record.uri?eid=2-s2.0-84893175011&doi=10.1109%2fMWSCAS.2013.6674807&partnerID=40&md5=f7572e89e63b24d3968cc90517b9a2a3 Anggraeni, S. and Hussin, F.A. and Jeoti, V. (2013) High throughput architecture for low density parity check (LDPC) encoder. In: UNSPECIFIED. http://eprints.utp.edu.my/32545/
institution Universiti Teknologi Petronas
collection UTP Institutional Repository
description This paper proposes a bit-wise matrix-vector multiplication in the optimization of a proposed low density parity check (LDPC) encoder. Investigation of this proposed architecture is done by implementing five code lengths using one IEEE 802.16e standard code rate. It is shown that the proposed architecture outperforms other works in terms of information throughput ranging from 0.235 to 8.83 times higher. In term of ratio of throughput per area, the proposed method exceeds other works in the range of 1.19 to 6.54 times higher. © 2013 IEEE.
format Conference or Workshop Item
author Anggraeni, S.
Hussin, F.A.
Jeoti, V.
spellingShingle Anggraeni, S.
Hussin, F.A.
Jeoti, V.
High throughput architecture for low density parity check (LDPC) encoder
author_sort Anggraeni, S.
title High throughput architecture for low density parity check (LDPC) encoder
title_short High throughput architecture for low density parity check (LDPC) encoder
title_full High throughput architecture for low density parity check (LDPC) encoder
title_fullStr High throughput architecture for low density parity check (LDPC) encoder
title_full_unstemmed High throughput architecture for low density parity check (LDPC) encoder
title_sort high throughput architecture for low density parity check (ldpc) encoder
publishDate 2013
url https://www.scopus.com/inward/record.uri?eid=2-s2.0-84893175011&doi=10.1109%2fMWSCAS.2013.6674807&partnerID=40&md5=f7572e89e63b24d3968cc90517b9a2a3
http://eprints.utp.edu.my/32545/
_version_ 1741197748478148608
score 11.62408

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